A serial peripheral interface (SPI) is commonly included in mobile devices to provide synchronous serial communication between a system-on-a-chip (SoC) processor and various peripheral devices. The SoC functions as an SPI master device whereas each peripheral device functions as a slave SPI device. An SPI bus couples the master device to each SPI slave devices. The master device supplies a clock to a clock line in the SPI bus. All serial data exchanges between the master device and the slave devices are synchronous to the clock signal. The master device drives data to the slave devices over a master-out-slave-in (MOSI) line. The slave devices may each drive data to the master on a shared master-in-slave-out (MISO) line. Since the MISO line is shared by the slave devices, the SPI bus also includes a slave select line for each slave device to provide an access protocol to the shared MISO line.
As each slave has its own the slave select line, the SPI bus at each slave device is a four-wire bus to accommodate the clock, MOSI, MISO, and slave select signaling. But the SPI bus at the master device will be a (3+N) wire bus, where N is an integer representing the number of slave devices Each wire in the SPI bus is dedicated to its own pin such that the number of pins at the master device dedicated to the SPI bus grows with the number of slave devices it services. As a result, fewer pins in a master device such as an SoC may be dedicated for other signaling. Moreover, each required additional pin on the master device raises manufacturing costs.
Accordingly, there is a need in the art for an improved SPI interface that alleviates the pin demands of conventional SPI architectures.